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A power amplifier is a core component that is to build a next generation communication system, and such a communication system needs a wide bandwidth to support a high data rate. It must be operated under switch mode to design a high efficiency power amplifier transistor, and / or have reflected termination harmonics. However, in order to lower the work of multiple octave bands at low frequencies, the in-band harmonics must end. In addition, the Boardfano theory of bandwidth, the load for a given compound may be in the presence of a base to perform bandlimiting to further reduce specific load impedance, from more efficient conditions.

We compare and compare two different broadband high efficiency power amplifier design techniques. Designed using non-uniformly distributed amplifier topology, complete MMIC, built into 50 Ω input and output match. In another design, we use an integrated hybrid design for bridge-T MMIC package input matching. In this paper, we first describe the circuit manufacturing process easily, then display it one by one and explain the topology of the design.

Based on AlGaN / GaN based HEMT device made with 100 mm SiC wafer TQGaN 25 TriQuint Co. 0.25 μm GaN process Power amplifier as used herein. This is because TriQuint has launched a large-scale manufacturing technology. PAE with a typical power density of 5.5 W / mm with a 4 finger transistor gate width of 100 μm (bias voltage: Vd = 40 V, ID = 100 mA / mm) with PAE matching condition, 60% PAE at 10 GHz.

In order to achieve maximum power and efficiency, the power amplifier selected the distributed power amplifier (NDPA) topology heterogeneously. Instead of NDPA, do not drain 50 Ω line termination impedance that uses the slope of the transmission line. To provide optimum load for each cell, select a specific width for each transmission line. In some cases, we also use the design of each unit element size gradient.

Since the operating frequency of the target power amplifier of 30 MHz to 2.7 GHz, we selected a 5 cell design, and to achieve power pin-hen, gain, bandwidth, and chip size, a total circumference of 2.4 mm It means Chang. After that, we calculated the size of the device and the impedance of the transmission line of each cell. The results are shown in Table 1. The size of the first cell, its purpose is to maximize power and efficiency, 1.2 mm. The size equal to the remaining cells is 0.3 mm. Please note that Table 1 as the drain current (Id) of each part. This current represents the maximum drive current of the device and sets the minimum width of the output trace.